Physical electronics devices and ics miscellaneous Easy Questions and Answers | Page - 20

Physical electronics devices and ics miscellaneous

The NMOS transistor has V_T = 0·7 V, µ_n C_OX = 100 µA/V², L = 1 µm, W = 32 µm. If I_D = 0·4 mA and V_D = 0·5 V. The values of R_D and R_S are respectively given by—

1. 5 Ω, 3·25 kΩ
1. 3·25 kΩ, 5 kΩ
1. 2·5 kΩ, 6·5 kΩ
1. None of these

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The given circuit

Given, V_T = 0·7 V, U_nC_ox = 100 µA/V²
L = 1 µm, W = 32 µm, I_D = 0·4 mA, V_D = 0·5 V
From figure,
or R_D = V_DD – V_D
I_D

= 2·5 – 0·5 = 5 kΩ
0·4 mA

Since, V_DS > V_GS, this means the NMOS transistor is operating in saturation region.
Now, I_D = 1 µn C_OX ×
W (V_GS – V_T) ²
2 L

V_GS – V_T = V_DS(Condition for saturation region)
or V_GS – V_T = 0·5 V
or V_GS = 0·5 + V_T = 1·2 V
or V_G – V_S = 1·2 V
or O – V_S = 1·2 V or V_S = 1·2 V
Now, R_S = V_S – V_SS =
– 1·2 V – (– 2·5 V)
I_D 0·4 mA

or R_S = 1·3 V = 3·25 kΩ
0·4 mA

Hence alternative (A) is the correct choice.

Correct Option: C

The given circuit

Given, V_T = 0·7 V, U_nC_ox = 100 µA/V²
L = 1 µm, W = 32 µm, I_D = 0·4 mA, V_D = 0·5 V
From figure,
or R_D = V_DD – V_D
I_D

= 2·5 – 0·5 = 5 kΩ
0·4 mA

Since, V_DS > V_GS, this means the NMOS transistor is operating in saturation region.
Now, I_D = 1 µn C_OX ×
W (V_GS – V_T) ²
2 L

V_GS – V_T = V_DS(Condition for saturation region)
or V_GS – V_T = 0·5 V
or V_GS = 0·5 + V_T = 1·2 V
or V_G – V_S = 1·2 V
or O – V_S = 1·2 V or V_S = 1·2 V
Now, R_S = V_S – V_SS =
– 1·2 V – (– 2·5 V)
I_D 0·4 mA

or R_S = 1·3 V = 3·25 kΩ
0·4 mA

Hence alternative (A) is the correct choice.

Consider the JFET circuit given below—
Current I_D is given by
Assume I_D = 12 1 + V_GS ² mA—
4

1. 2·26 mA
1. 3·39 mA
1. 1·48 mA
1. 2·78 mA

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The given circuit

From given circuit V_GS = V_G – V_S = 0 – V_S
(Since V_G = 0V and V_S = I_DR_S)
or V_GS = – I_DR_S = – I_D.1 kΩ

Now, I_D = 12 1 + V_GS ² mA

4

Now, I_D = 12 1 - I_D ²

4

or I_D = 12 1 + I_D² – 2.1. I_D
16 4

or I_D = 12 16 + I_D² – 8I_D
16

or 4 I_D = 48 + 3 I_D²– 24 I_D
or 3 I_D² – 28 I_D + 48 = 0
or I_D = 28 ± √28₂ – 4 × 3 × 48
2 x 3

I_D = 2·26 mA
Hence alternative (A) is the correct choice.

Correct Option: A

The given circuit

From given circuit V_GS = V_G – V_S = 0 – V_S
(Since V_G = 0V and V_S = I_DR_S)
or V_GS = – I_DR_S = – I_D.1 kΩ

Now, I_D = 12 1 + V_GS ² mA

4

Now, I_D = 12 1 - I_D ²

4

or I_D = 12 1 + I_D² – 2.1. I_D
16 4

or I_D = 12 16 + I_D² – 8I_D
16

or 4 I_D = 48 + 3 I_D²– 24 I_D
or 3 I_D² – 28 I_D + 48 = 0
or I_D = 28 ± √28₂ – 4 × 3 × 48
2 x 3

I_D = 2·26 mA
Hence alternative (A) is the correct choice.

Moor’s law is related to—

1. Speed of operation of bipolar device
1. Speed of operation of MOS devices
1. Power rating of MOS devices
1. Level of integration of MOS devices

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Moor’s law is related to level of integration of MOS devices.

Correct Option: D

Moor’s law is related to level of integration of MOS devices.

Match List-I (State of operation of an N-MOSFET) with List-II (Required condition) and select the correct answer using the code given below the lists—
List-I
(a) OFF
(b) Linear region
(c) Non-linear
(d) Saturation region
List-II
1. V_gs > V_th and V_ds < (V_gs – V_th)
2. V_gs > V_th and V_ds > (V_gs – V_th)
3. V_gs > V_th
4. V_gs < V_th
The correct code is—

1. 2314
1. 4132
1. 2134
1. 4312

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N-MOSFET
● OFF → When V_gs < V_th
● Linear region → When V_gs > V_th and V_ds < (V_gs – V_th)
● Non-linear → When V_gs > V_th
● Saturation → When V_gs > V_th and Vas > (V_gs region – V_th)

Correct Option: B

N-MOSFET
● OFF → When V_gs < V_th
● Linear region → When V_gs > V_th and V_ds < (V_gs – V_th)
● Non-linear → When V_gs > V_th
● Saturation → When V_gs > V_th and Vas > (V_gs region – V_th)

Consider the following statements—
1. The threshold voltage (V_T) of a MOS capacitor decreases with increase in gate oxide thickness.
2. The threshold voltage (V_T) of a MOS capacitor decreases with increase in substrate doping concentration. Which of the statements given above are correct.

1. 1 is FALSE and 2 is TRUE
1. Both 1 and 2 are TRUE
1. Both 1 and 2 are FALSE
1. 1 is TRUE and 2 is FALSE

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The threshold voltage of N-channel MOSFET is expressed by
V_TN = |Q’_SD(max)| -
Q’_ss + φ_ms + 2φ_fp
C_ox C_ox

Where, V_TN = Threshold voltage for N-MOSFET
Q’_ss = Electronic charge perunit area
φ_ms = Work function difference
_φfp = Surface potential

e = Charge of electron
∈_s = Permitivity
N_a = Acceptor ion concentration
C_ox = ∈_ox
t_ox

t_ox = gate oxide thickness
Thus on increasing gate oxide thickness. C_ox decreases which increase threshold voltage, V_TN.
And the threshold voltage V_TN of a MOS capacitor with increase in substrate doping concentration increases,
since VTN α √N_a
Hence alternative (A) is the correct choice.

Correct Option: A

The threshold voltage of N-channel MOSFET is expressed by
V_TN = |Q’_SD(max)| -
Q’_ss + φ_ms + 2φ_fp
C_ox C_ox

Where, V_TN = Threshold voltage for N-MOSFET
Q’_ss = Electronic charge perunit area
φ_ms = Work function difference
_φfp = Surface potential

e = Charge of electron
∈_s = Permitivity
N_a = Acceptor ion concentration
C_ox = ∈_ox
t_ox

t_ox = gate oxide thickness
Thus on increasing gate oxide thickness. C_ox decreases which increase threshold voltage, V_TN.
And the threshold voltage V_TN of a MOS capacitor with increase in substrate doping concentration increases,
since VTN α √N_a
Hence alternative (A) is the correct choice.