Analog electronics circuits miscellaneous Easy Questions and Answers | Page - 23

Analog electronics circuits miscellaneous

In the circuit given below the transistor parameters are
V_TN = 1 V, and k_n = 36 µA/V². If I_D = 0.5 mA, V₁ = 5 V and V₂ = 2 V then the width-to-length ratio
i.e. W required in each transistor is
L

W W W
L ₁ L ₂ L ₃

1. 1.75, 6.94, 27.8
1. 4.93, 10.56, 50.43
1. 35.4, 22.4, 8.53
1. 56.4, 38.21, 12.56

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For each transistor M₁, M₂ and M₂
V_GS = V_DS i.e. V_DS > V_GS – V_TN
Therefore all the transistor are in saturation Given that
V_TN = 1 V
k′_n = 36 µA/V²
I_D = 0.5 mA
V₁ = 5 V_S V₂ = 2 V
For transistor M₃
V₂ = 2V = V_GS₃
I_D = 0.5 × 10^–3
= 1 36 × 10^–6 W . (2 – 1)²
2 L ₃

after simplifying we get W = 27.8
L ₃

For transistor M₂,
V_GS₂ = V₁ – V₂ = 5 – 2 = 3 V
I_D = 0.5 × 10^–3
= 36 × 10^–6 W (3 – 1)²
L ₂

or W = 6.94
L ₂

For transistor M₁
V_{GS₁ = 10 – V₁ = 10 – 5 = 5 V
I_D = 0.5 × 10^–3
= 1 36 × 10^–6 W . (5 – 1)²
2 L ₁

or W = 1.74
L ₁

Hence alternative (A) is the correct choice.}

Correct Option: A

For each transistor M₁, M₂ and M₂
V_GS = V_DS i.e. V_DS > V_GS – V_TN
Therefore all the transistor are in saturation Given that
V_TN = 1 V
k′_n = 36 µA/V²
I_D = 0.5 mA
V₁ = 5 V_S V₂ = 2 V
For transistor M₃
V₂ = 2V = V_GS₃
I_D = 0.5 × 10^–3
= 1 36 × 10^–6 W . (2 – 1)²
2 L ₃

after simplifying we get W = 27.8
L ₃

For transistor M₂,
V_GS₂ = V₁ – V₂ = 5 – 2 = 3 V
I_D = 0.5 × 10^–3
= 36 × 10^–6 W (3 – 1)²
L ₂

or W = 6.94
L ₂

For transistor M₁
V_{GS₁ = 10 – V₁ = 10 – 5 = 5 V
I_D = 0.5 × 10^–3
= 1 36 × 10^–6 W . (5 – 1)²
2 L ₁

or W = 1.74
L ₁

Hence alternative (A) is the correct choice.}

Direction: Consider the circuit shown below:
The both transistor have parameter as follows:
V_TN = 0.8 V, k_n = 30 ΩA/V²

If the ratio is W = 40 and W = 15, then V₀ is:
L ₁ L ₂

1. 2.91 V
1. 2.09 V
1. 3.41 V
1. 1.59 V

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According to question
W = 40 and W = 15
L ₁ L ₂

Again
K_n₁ (V_GS₁ – V_TN₁ )2=K_n₂ (V_GS₂ – V_TN₂ )2
40 (V_GS₁ – 0.8)2 = 15 (V_GS₂ – 0.8)2 `…(A)
V_GS₁ + V_GS₂ = 5 …(B)
from (A) and (B)
40 (V_GS₁ – 0.8)2 = 15 (5 – V_GS₁ – 0.8)2
8 [V²_GS₁ +.64 –1.6 V_GS₁] = 3 [17.64 + V²_GS₁ –8 V_GS₁]
5 V²_GS₁ + 11.2 V_GS₁ – 47.8 = 0
V_GS₁ = 2.09
V₀ = 5 – V_GS₁
= 5 – 2.09 = 2.91 V

Correct Option: A

According to question
W = 40 and W = 15
L ₁ L ₂

Again
K_n₁ (V_GS₁ – V_TN₁ )2=K_n₂ (V_GS₂ – V_TN₂ )2
40 (V_GS₁ – 0.8)2 = 15 (V_GS₂ – 0.8)2 `…(A)
V_GS₁ + V_GS₂ = 5 …(B)
from (A) and (B)
40 (V_GS₁ – 0.8)2 = 15 (5 – V_GS₁ – 0.8)2
8 [V²_GS₁ +.64 –1.6 V_GS₁] = 3 [17.64 + V²_GS₁ –8 V_GS₁]
5 V²_GS₁ + 11.2 V_GS₁ – 47.8 = 0
V_GS₁ = 2.09
V₀ = 5 – V_GS₁
= 5 – 2.09 = 2.91 V

If the width-to-length ratios of M₁ and M₂ are:
W = W = 40
L ₁ L ₂

The output V₀ is:

1. 1.5 V
1. 2.5 V
1. 5 V
1. 0 V

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For both transistor M₁ and M₂
V_DS = V_GS
∴ V_DS > V_GS – V_TN therefore both the transistor are in saturation
I_D₁ = I_D₂
I_D₁ = K_n₁ (V_GS₁ – V_TN₁ )²
= K_n₂ (V_GS₂ – V_TN₂)² …(A)
K_n₁ = K_n₂ and V_TN₁ = V_TN₂
on expanding equation
V²_GS₁ + V²_TN₁ – 2V_GS₁ = V²_GS₂ + V²_TN₂ – 2V_GS₂
or V²_GS₁ + V²_GS₂ = 2 (V_GS₁ – V_GS₂) …(B)
from given figure,
V_GS₁ + V_GS₂ = 5 …(C)
V²_GS₁ – (5 – V_GS₁ )2 = 2 (V_GS₁ – V_GS₁ + 5)
V²_GS₁ – 25 – V²_GS₁ + 10 V_GS₁ = 10
10 V_GS₁ = 35
or V_GS₁ = 3.5
V_GS₂ = 5 – V_GS₁ = 5 – 3.5 = 1.5 V
So, V₀ = 5 – V_GS₁ = V_GS₂ = 1.5 V

Correct Option: A

For both transistor M₁ and M₂
V_DS = V_GS
∴ V_DS > V_GS – V_TN therefore both the transistor are in saturation
I_D₁ = I_D₂
I_D₁ = K_n₁ (V_GS₁ – V_TN₁ )²
= K_n₂ (V_GS₂ – V_TN₂)² …(A)
K_n₁ = K_n₂ and V_TN₁ = V_TN₂
on expanding equation
V²_GS₁ + V²_TN₁ – 2V_GS₁ = V²_GS₂ + V²_TN₂ – 2V_GS₂
or V²_GS₁ + V²_GS₂ = 2 (V_GS₁ – V_GS₂) …(B)
from given figure,
V_GS₁ + V_GS₂ = 5 …(C)
V²_GS₁ – (5 – V_GS₁ )2 = 2 (V_GS₁ – V_GS₁ + 5)
V²_GS₁ – 25 – V²_GS₁ + 10 V_GS₁ = 10
10 V_GS₁ = 35
or V_GS₁ = 3.5
V_GS₂ = 5 – V_GS₁ = 5 – 3.5 = 1.5 V
So, V₀ = 5 – V_GS₁ = V_GS₂ = 1.5 V

The parameters for the transistor in circuit of fig. below are V_TN = 2 V and K_n = 0.2 mA/V². The power dissipated in the transistor is:

1. 5.84 mW
1. 2.34 mW
1. 0.26 mW
1. 58.4 mW

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From fig. since gate is connected to the drain. Hence transistor will always in saturation.
I_D = 10 – V_GS = K_n (V_GS – V_Tn)²
10 kΩ

10 – V_GS = 0.2 × 10^–3 × 10 × 10³ (V_GS – 2)²
or 10 – V_GS = 2 (V_GS – 2)²
After solving quadratic equation, we get
V_GS = – 0.27 V, 3.77 V V_GS = – 0.27 is not possible since gate terminal is at 10 V. So, V_GS = 3.77 V is taken
i.e. V_GS = V_DS = 3.77 V
I_D = 10 – 3·77 = 0.623 mA
10 kΩ

Power = I_D V_DS = 0.623 × 10^–3 × 3.77 = 2.35 mW

Correct Option: B

From fig. since gate is connected to the drain. Hence transistor will always in saturation.
I_D = 10 – V_GS = K_n (V_GS – V_Tn)²
10 kΩ

10 – V_GS = 0.2 × 10^–3 × 10 × 10³ (V_GS – 2)²
or 10 – V_GS = 2 (V_GS – 2)²
After solving quadratic equation, we get
V_GS = – 0.27 V, 3.77 V V_GS = – 0.27 is not possible since gate terminal is at 10 V. So, V_GS = 3.77 V is taken
i.e. V_GS = V_DS = 3.77 V
I_D = 10 – 3·77 = 0.623 mA
10 kΩ

Power = I_D V_DS = 0.623 × 10^–3 × 3.77 = 2.35 mW

The PMOS transistor shown below has parameters:
V_TP = - 1.2 V, W = 20, and K_P = 30 µA/V²
L

If I_D = 0.5 mA and V_D = – 3 V, then value of R_S and R_D are:

1. 4 kΩ, 5.8 kΩ
1. 4 kΩ, 5 kΩ
1. 5.8 kΩ, 4 kΩ
1. 5 kΩ, 4 kΩ

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NA

Correct Option: D

NA