Advanced Microprocessors
- Given Boolean theorem AB + A′C + BC = AB + A′C which of the following is true?
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For the given Boolean theorem
AB + A′C + BC = AB + A′C
Apply dual property, we get:
(A + B) (A′ + C) (B + C) = (A + B) (A′ + C)
Hence alternative (A) is the correct answer.Correct Option: A
For the given Boolean theorem
AB + A′C + BC = AB + A′C
Apply dual property, we get:
(A + B) (A′ + C) (B + C) = (A + B) (A′ + C)
Hence alternative (A) is the correct answer.
- (A′ + B′ + C′)′ is equal to—
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= (A′ + B′ + C′)′
= A′′. B′′. C′′
= ABC
Hence (B) is the correct alternative.Correct Option: B
= (A′ + B′ + C′)′
= A′′. B′′. C′′
= ABC
Hence (B) is the correct alternative.
- Which of the following indentities is true?
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Apply hit and trial method
(A) A + AC + AB + BC = A + BC: i.e., False
(B) AC + AB + BC: i.e., False
(C) AC + AB + BC = AC + AB = BC + AA = A (A + B) + C (A + B) = (A + C) (A + B)
which is ≠ LHS i.e., False
(D) A + AC + AB + BC
= A (1 + C) + AB + BC
= A + BC
= L.H.S. True
Hence alternative (D) is the correct answer.Correct Option: D
Apply hit and trial method
(A) A + AC + AB + BC = A + BC: i.e., False
(B) AC + AB + BC: i.e., False
(C) AC + AB + BC = AC + AB = BC + AA = A (A + B) + C (A + B) = (A + C) (A + B)
which is ≠ LHS i.e., False
(D) A + AC + AB + BC
= A (1 + C) + AB + BC
= A + BC
= L.H.S. True
Hence alternative (D) is the correct answer.
- A microprocessor with a 16 bit address bus is used in a linear memory selection configuration (i.e., Address bus lines are directly used as chip select of memory chips) with 4 memory chips. The minimum addressable memory space is—
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Each bit require one line so that for n lines, the size of memory in the address bus is 2n
for 16 bit, 216 = 65, 536 or 64 K.Correct Option: A
Each bit require one line so that for n lines, the size of memory in the address bus is 2n
for 16 bit, 216 = 65, 536 or 64 K.
- In a dual slope ADC, to eliminate 50 Hz pick up, the minimum period of integration of the input signal is adjusted to be …… ms.
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The gate period is made equal to main supply period, 1/50 = 0·02 s or 20 ms. for 60 Hz, it is 16·67 ms.
Correct Option: B
The gate period is made equal to main supply period, 1/50 = 0·02 s or 20 ms. for 60 Hz, it is 16·67 ms.