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Computer organization and architecture miscellaneous

Computer Organization and Architecture

Direction: Consider a machine with a 2-way set associative data cache of size 64 kbyte and block size 16 byte. The cache is managed using 32 bit virtual addresses and the page size is 4 kbyte. A program to be run on this machine begins as follows.
double ARR [1024] [1024]
    int i, j;
   /* Initialize array ARR to 0.0 */
   for (i = 0; i < 1024; i ++)
   for (j = 0; j < 1024; j ++)
   ARR [i] [j] = 0.0;
The size of double is 8 byte. Array ARR is located in memory starting at the beginning of virtual page 0 × FF000 and stored in row major order. The cache is initially empty and no pre-fetching is done. The only data memory references made by the program are those to array ARR.

  1. The cache hit ratio for this initialization loop is
    1. 0%
    2. 25%
    3. 50%
    4. 75%
Correct Option: C

Block size = 16B and one element = 8B, So in one block 2 element will be stored.
For 1024 * 1024 element num of block required = 1024 *1024/2 = 2^19 blocks required. In one block first element will be a miss and second one is hit (since we are transferring two unit at a time).

⇒ hit ratio =
total hit
total reference

=
2^19
=
1
= 0.5
2^202

= 0. 5 * 100 = 50%



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